3D Stacked Transistors: Improving Area By Building Upward

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Published May 6, 2025

The pursuit of increased performance and transistor density will be realized not just by making transistors smaller, but also through novel designs and structures. Intel Component Research Engineer, Marko Radosavljevic, uses augmented reality to walk through several years of Intel breakthroughs demonstrating the development of 3D stacking techniques that will be able to reduce a chip’s logic footprint. Learn more: https://intel.ly/3EPDvG6

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3D Stacked Transistors: Improving area by building upward | Intel Technology
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